Simulation-Based Functional Test Generation for Embedded Processors
Hung-Pin (Charles) Wen, opwen@ece.ucsb.edu, Li-C. Wang, Kwang-Ting Cheng, Univ. of California, Santa Barbara, CA

Scalable Defect Mapping and Configuration of Memory-Based Nanofabrics
Chen He, che@ece.utexas.edu, Univ. of Texas, Freescale Semiconductor, Inc., Austin TX, Margarida F. Jacome, Gustavo de Veciana, Univ. of Texas, Austin, TX

Improvement of Fault Injection Techniques Based on VHDL Code Modification
Joaquin Gracia, jgracia@disca.upv.es, Daniel Gil, Juan C. Baraza, Pedro J. Gil, Universidad Poltecnica de Valencia, Valencia, Spain

MVP: A Mutation-Based Validation Paradigm
Jorge Campos, jcampos@ucdavis.edu, Hussain Al-Asaad, Univ. of California, Davis, CA

Sequential Equivalence Checking Based on K-th Invariants and Circuit SAT Solving
Feng Lu, lufeng@ece.ucsb.edu, Tim Cheng, Univ. of California, Santa Barbara, CA

VERISEC: VERIfying Equivalence of SEquential Circuits using SAT
Manan Syal, mysal@vt.edu, Intel Corp.,Hillsboro, OR, Michael S. Hsiao, Virginia Tech., Blacksburg, VA

Automated Clock Inference for Stream Function-Based System Level Specifications
Sandeep K. Shukla, shukla@vt.edu, Virginia Tech., Blacksburg, VA, Jean-Pierre Talpin, IRISA/INRIA, Rennes, France

Cosimulation of ITRON-Based Embedded Software with SystemC
Shin-ichiro Chikada, chikada@ertl.jp, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada, Nagoya Univ., Aichi, Japan

Stimulus Generation for Interface Protocol Verification Using the Non-Deterministic Extended Finite State Machine Model
Che-Hua Shih, matar@eda.ee.nctu.edu.tw, Juinn-Dar Huang, Jing-Yang Jou, National Chiao Tung Univ., Hsinchu, Taiwan, ROC

A Test Generator for the Transmeta Efficeon VLIW Processor
Kevin D. Rich, kdrich@transmeta.com, Shankar Govindaraju, Robert Shaw, David Dobrikin, Transmeta Corp., Santa Clara, CA

Session 5: Validation Test Generation II

Reuse in System-Level Stimuli-Generation
Shady Copty, shady@il.ibm.com, Itai Jaeger, Yossi Lichtenstein, Yoav Katz,
IBM Haifa Research Labs, Haifa, Israel, Anita Devadason, Audrey Romonosky, IBM Corp., Austin, TX

Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation
Ari Frueng, arief@il.ibm.com, Shai Fine, Itai Jaeger, Yehuda Naveh, Avi Ziv, IBM Haifa Research Labs, Haifa, Israel, Yishay Mansour, Tel Aviv Univ., Tel Aviv, Israel

Session 6: New Approaches in Simulation

A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal
Qingwei Wu, qiwu@cadence.com, Cadence Design Systems, Inc., San Jose, CA,
Michael S. Hsiao, Virginia Tech., Blacksburg, VA

Validating Families of Latency Insensitive Protocols
Syed Suhaib, ssuhaib@vt.edu, Deepak Mathaikutty, Sandeep Shukla,
Virginia Tech., Blacksburg, VA, David Berner, INRIA-IRISA, France

GASIM: A Fast Galois Field Based Simulator for Functional Model
Ashutosh Kumar Singh, ashutosh@unitar.edu.my, UNITAR, Selangor Darul Ehsan, Malaysia, Dhiraj K. Pradhan, Univ. of Bristol, Bristol, United Kingdom, T.L. Rajaprabhu, Georgia Institute of Tech., Atlanta, GA, Abusaleh M. Jabir, Oxford Brookes Univ., Oxford, United Kingdom

Overlap Reduction in Symbolic System Traversal
Prakash Mohan Perariandam, prakash@informatik.uni-tuebingen.de, P.K. Nalla,
R.J. Weiss, J. Ruf, T. Kropf, W. Rosenstiel, Univ. of Teubingen, T Chia-Chih Yen, jackr@eda.ee.nctu.edu.tw, Jing-Yang Jou, National Chiao-Tung Univ., Hsinchu, Taiwan

Increasing the Deductibility in CNF Instances for Efficient SAT-based Bounded Model Checking
Vishnu C. Vimjam, vvimjam@vt.edu, Michael S. Hsiao, Virgina Tech., Blacksburg, VA

B-Cubing Theory: New Possibilities for Efficient SAT-Solving
Alan J. Hu, ajh@cs.ubc.ca, Domagoj Babic, Jesse Bingham,
Univ. of British Columbia, Vancouver, BC, Canada

Multi-level Design Validation in a Secure Embedded System
David D. Hwang, dhwang@ee.ucla.edu, Shenglin Yang, Ingrid Verbauwhede, Univ. of California, Los Angeles, CA, Patrick Schaumont, Virginia Tech., Blacksburg, VA

Security Evaluation Against Electromagnetic Analysis at Design Time
Huiyun Li, huiyun.li@cl.cam.ac.uk, Theodore Markettos, Simon Moore, Univ. of Cambridge, Cambridge, United Kingdom

Functional Coverage: Is Your Design Exposed?

Moderator: Andrew Piziali - Cadence Design Systems, Verification Application Specialist, Plano, TX

Panelists:

Neyaz Khan - Cadence Design Systems, Plano, TX
Laurent Fournier - IBM, Haifa, Israel
Gery Osowiecki - Texas Instruments, Plano, TX
Tom Anderson - Synopsys, San Jose, CA
Michael Bair - Intel, Hillsboro, OR